The present invention relates to a method and/or architecture for bus interfaces generally and, more particularly, to a method and/or architecture for reducing power consumption and simultaneous switching in a bus interface.
Conventional approaches simply present data on a bus interface. The power consumption and switching overhead is consumed accordingly. Conventional approaches consume (i) more power and (ii) introduce more simultaneous switching than necessary.
The present invention concerns an apparatus comprising a transmit portion and a receive portion. The transmit portion may be configured to present (i) one or more data signals and (ii) a configuration signal, in response to one or more input signals. The receive portion may be configured to receive (i) all of the one or more data signals when operating in a first mode and (ii) less than all of the data signals when operating in a second mode. The first and second modes may be configured in response to the configuration signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a bus interface that may (i) replace an existing bus, while maintaining the same frequency, of operation, (ii) reduce power consumption, (iii) improve system noise immunity, (iv) reduce it a number of and/or a voltage level of power pads and/or (v) provide a simplified board layout.